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Altera_Forum
Honored Contributor
Honored ContributorBug: Dynamic PLL phase shifting breaks clock compensation
We have just finished producing some prototype cards based on the Arria V GX (5AGXMA3D4F27C5) and have a problem with the fPLL behaviour. The setup is as follows: 1- An 125MHz input clock (N1...
Altera_ForumHonored Contributor
Honored ContributorI've found the fix to this problem. The arria5 fPLL needs to be manually reset upon device power-up. The "auto-reset" in the megawizard doesn't do the job. Once I manually reset the fPLL, the clocks lined up like a charm.
