Hi, I require clocks with different phase shifts. Theoretically, the outputs at each stage of the buffers in the buffer chain of DLL in ALTDLL megafunction should do it. However, ALTDLL outputs only dll_delayctrlout and the buffer clock outputs are not available. Is there any way to access them? Thanks.

I'm fairly certain the DLL is dedicated silicon for a specific function, and therefore only has one driver output. Why not use a PLL?

DLL had delay elements (buffers) which shift the phase of the clock(as shown in the image attached). The application requires me to have a clock with 8 synchronized phase delays (i.e. 45,90,....,360). I am getting the desired frequency of the clock using PLL; however, to get these phase delays, I need to use a DLL. Yes, it is possible to achieve the same using PLL by having a high-speed clock and then using digital logic and get the required number of slower phase delayed clocks. I'm trying to avoid this option as PLL output at that high frequency is not permissible on the DE4 board. It would be much easier if I could somehow get the buffer outputs instead.

Not sure what device you're looking at, but usually those delaytaps go directly into a mux and only one is selected. There is not an individual driver for each one into the fabric. For multiple phases, users generally take a PLL and have it's outputs drive 0/45/90/135 and then invert it(which is done for free at the LAB level) for the other phases. There is no digital logic, as the PLL has multiple counter outputs.

Thanks for the answer! The suggested method will work, except for one problem: the inverters will add a finite delay in addition to providing 180 phase shift to 0/45/90/135 clocks. This delay might be a problem for the required high-speed application. Just for clarification, to implement 45/90/135 phase delays, I would need to drive three different DLL's using PLL output, right? The device I'm using is Stratix IV board, with Quartus prime standard edition software.

No, no DLL at all. Just a single PLL with four outputs. What speeds? If I were to guess you plan on capturing your data input with 8 phase of the clock and having some logic to determine the right phase? The delay of a NOT gate is negligible. It's not done through a LUT but through a dedicated inversion going into the LAB, so it's probably less than 20ps. There are all sorts of other things that are going to hurt you. First, the PLL has to drive global clock trees. So if you drive four global clock trees, they will naturally have a decent amount of on-die variation, just because they are so large. Next, there are only three clock lines per LAB, so at most you're get 3/8 clocks into a LAB. So you'll really be driving three different LABs. There will be sizable delays in your datapath to each LAB, much larger than the NOT gate. Finally, if you can get it all correct and have minimal variation, you'll need to lock down the placement and routing. All very difficult. Is your IO standard LVDS? Could you use the dedicated altlvds silicon which can overclock it at a very high rate, and then once it's parallelized you can do what you want with the logic?

Buffer chain output from DLL in ALTDLL | Altera Community

12 Replies

Altera_Forum
Honored Contributor
8 years ago
If you go down to 150MHz, then a lot more is possible. I'm guessing you can do it with PLL outputs and it should work. But you do need to monitor the timing on the place-and-route, as it can change compile to compile.
When you say altlvds at 1500Mps isn't possible, how come? Note that altlvds has a PLL in it, so you could, for example, drive it with a 150MHz clock, then internally that would crank it up 8x to a 1200Mbps sampling clock, and then deserialize it /8 back to 8-bits of data coming out at 150MHz. Since it's dedicated silicon, it would all be laid out properly and not change compile to compile.
Altera_Forum
Honored Contributor
8 years ago
Oh, okay. I am going to try the altlvds_rx first.
I am grateful that you spent your time on this discussion. Thanks a lot!

Forum Discussion

Buffer chain output from DLL in ALTDLL

12 Replies

Recent Discussions

Timing Slacks inside Altera IP

Part Status request

Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Vcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0

Arria 10: Remote Update Factory Fallback won't work & Watchdog does not trigger