Forum Discussion
Altera_Forum
Honored Contributor
8 years agoThanks for the answer! The suggested method will work, except for one problem: the inverters will add a finite delay in addition to providing 180 phase shift to 0/45/90/135 clocks. This delay might be a problem for the required high-speed application.
Just for clarification, to implement 45/90/135 phase delays, I would need to drive three different DLL's using PLL output, right? The device I'm using is Stratix IV board, with Quartus prime standard edition software.