Hello again, I am still struggling with BPSK demodulation :) OK, now I am trying to implement Costas Loop for carrier synchronization, which involves Inphase and Quadrature Phase paths. Inphase is looking good, and works as expected, however, the Q component looks awkward. Take a look at these waveforms: http://www.alteraforum.com/forum/attachment.php?attachmentid=10363&stc=1 I understand that multiplying sin * cos will produce a high frequency component, which is a sin modulated by half amplitude of the data signal. BPSK(t) * sin(2*pi*f*t) = 0.5 * [DATA(t) * sin(0) + DATA(t) * sin(2*pi*f*t)] => 0.5 * DATA(t) * sin(2*pi*f*t) => LPF{0.5 * DATA(t) * sin(2*pi*f*t)} = 0 I feel that problem is in my LPF. I used the same Matched RRC filter that I used in the in-phase arm. Papers I read didn't mention that these two filters should be different, that's why I used the same filter. (I think those are unpractical DSP writers, KAZ :D ) So, should I use a separate Loop Filter for Q component? How do I determine it's parameters?

How did you design the costas loop? How do you control the loop> loop filter has to be separate filter from rrc. You will use it to control the lock of your costas loop and usually a simple IIR will do I have used rrc after costas locking section but I know some do it before but not as loop filter (there are different rx configurations and you better model it matlab before going to hardware).

I am sorry, it's my mistake... I didn't mention that after multiplication there is CIC filter... before RRC. So these are the waveforms: https://www.alteraforum.com/forum/attachment.php?attachmentid=10365 Basically, I am trying to design this loop: https://www.alteraforum.com/forum/attachment.php?attachmentid=10366 Instead of LPF, I used CIC filters, as they do filtering and decimation at the same time. Am I wrong? You are right, RRC has nothing to do with Costas Loop.

You need one filter per branch to remove the f1+f2 (sum term) leaving signal at dc (f1-f2). Any LPF will do (including rrc if you wish). The loop itself needs error detector and filter to smooth out the error. This loop filter can be an IIR with variable gain. The IIR filter represents the integral part of your loop control system. You may need further control terms such as proportional term. The filter error is then used to shift phase(or frequency) of NCO in the opposite sense. It takes sometime for the loop to lock. You observe the error and this should converge and settle with low jitter. I notice your bb_signal_I has plenty of zeros in it but not Q I wouldn't advice you to do any decimation inside loop as it could get complicated on you.

--- Quote Start --- You need one filter per branch to remove the f1+f2 (sum term) leaving signal at dc (f1-f2). Any LPF will do (including rrc if you wish). The loop itself needs error detector and filter to smooth out the error. This loop filter can be an IIR with variable gain. The IIR filter represents the integral part of your loop control system. You may need further control terms such as proportional term. The filter error is then used to shift phase(or frequency) of NCO in the opposite sense. --- Quote End --- The error detector you referred to is the mixer at the end of the loop, right? Regarding loop filter, I saw some structures that combine both integral and proportional terms, is it the same as you are suggesting? http://www.alteraforum.com/forum/attachment.php?attachmentid=10367&stc=1 --- Quote Start --- I notice your bb_signal_I has plenty of zeros in it but not Q --- Quote End --- You mean zero crossings? is this bad? --- Quote Start --- I wouldn't advice you to do any decimation inside loop as it could get complicated on you. --- Quote End --- I thought decimating is beneficial before doing any further signal processing as this relaxes the requirements. I'll use regular LPFs then. How to choose the cutoff frequency of these LPFs?

The bb_I difference from bb_Q may be due to your nco phase. For now assume it is ok and focus on cutting off the f1+f2 term in each branch. The wanted signal will move close to dc and depending on your signal bandwidth. you need to cutoff clear of your signal bandwidth but kill the f1+f2 copy. So far you have downconverted your signal to dc but now and since signal centre may shift either side of dc due to uncertainties of oscilillators bewteen Tx and Rx you need to force it to dc all the time. The error detector is just a multiplier as you have found out. apply IIR LPF (integrator) to the error as it will be very noisy. The gain of IIR need to be manually adjusted until error shows dampened oscillations heading towards zero with some jitter. For testing you will need to move your RF centre either side and see that the loop does not lose lock otherwise the radio user will have to keep adjusting the tuning knob and lose interest in music. If your loop fails to lock try adding the proportional term to the output of IIR through a scaler that can be adjusted.

BPSK Demodulation | Altera Community

66 Replies

Altera_Forum
Honored Contributor
11 years ago
1- Isn't that the supposed situation? I mean, I am expected to provide a fixed frequency and the carrier synchronizer has the job of recovering the phase, isn't it?
2- Do I understand that the first design (sin*cos) tracks phase only, while the above design (using sign circuitry) tracks frequency?
3- Surprisingly, before you post I was trying to simulate this design using my original BPSK signal, and the above design failed to demodulate properly even though the loop locked. I eventually did as you mentioned, I used the sin*cos approach and eliminated the "Phase Accumulator" and used the PhErr signal to control NCO. It did demodulate and lock! I tried to shift the local NCO phase and tried to set fc at 0.050001 (TX's fc is 0.05) and it locked.
Altera_Forum
Honored Contributor
11 years ago
There is here misunderstanding and it is difficult.
A true receiver (for wireless QAM) needs first to have clock recovery circuit to lock to Tx clock and this is a nightmare.

Once clock is recovered then other things are clocked by this pace maker.

The carrier tracking at Rx needs to lock to both rf frequency and phase. You may know the nominal Tx frequency centre but due to oscillator jitter and shift at both ends (and any mobile Rx) it will have to follow it. The phase must also lock at least in one qaudrant terms(1 of 4 quadrants for a cycle). It is no good locking to same freq but a changing or tilted phase.

The difficulty here is to understand these two concepts (freq and phase). If you can control phase of two different freqs you control both. freq and phase. If you control freq only you control freq ONLY.

some designs control either or both.

Your 1st design requires somebody else to control freq (apparently as we couldn't see any useful sense of error to be useful to push signal to baseband) but if given two inputs at same freq centre then it does give enough error to lock to one quadrant of cycle.

To test it keep rf and nco freqs at .1 then change the phase rf and see error.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
The difficulty here is to understand these two concepts (freq and phase). If you can control phase of two different freqs you control both. freq and phase. If you control freq only you control freq ONLY.
--- Quote End ---

This exactly what I'm doing and think I've done. Costas loop is meant to give PHASE error which happens to be very sensitive to small differences (2 times delta theta). And as you've just said, controlling phase means controlling both freq and phase.

--- Quote Start ---

Your 1st design requires somebody else to control freq (apparently as we couldn't see any useful sense of error to be useful to push signal to baseband) but if given two inputs at same freq centre then it does give enough error to lock to one quadrant of cycle.

To test it keep rf and nco freqs at .1 then change the phase rf and see error.
--- Quote End ---

The later design is pretty much the first one except that I used a loop filter now, and it seemed that I tested phase offsets in a wrong way in the first design (maybe it was good and working... anyway, this is better).

I tested as you said, I set RF and NCO at 0.05, then changed the phase of NCO by pi/8, pi/7, pi/3 and it demodulated and locked in all tests.
Do I say Yuppie now? :D
Altera_Forum
Honored Contributor
11 years ago
Yuppie Yupp. Is that Uni project? I won't tell anybody
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Yuppie Yupp. Is that Uni project? I won't tell anybody
--- Quote End ---

Yuppieeeeeeeeeeeeeeeeeeeeee!! I am always afraid from your comments to have my designs wrong LOL! But this one is the best :D
Yes it is my graduation project... Titled "SoC FPGA-Based Software-Defined Radio" and I think you deserve to mention your name in the thanks page :D
Why won't you tell anybody? Hhhhhhhhhh

Altera_Forum

Honored Contributor

9 years ago

Hi,

In this one, you are using a rf-signal (cosine wave). How this one can be BPSK signal?

1.What is inside RRC.mat?

2.How did you choose Bandwith = 200 hz.

Please reply to my questions.

--- Quote Start ---

Hello Kazem :)

I think I did it this time. Please take your time and test it at your leisure before judging :D


clear
clc
load RRC.mat
fc = 0.1 % 0.11  %0.09
rf_signal = cos(2*pi*(1:5000)*0.1);
N = length(rf_signal);
bb = zeros(1, N);
bb_f = zeros(1, N);
I_f = zeros(1, N);
Q_f = zeros(1, N);
I_r = zeros(1, N);
Q_r = zeros(1, N);
error = zeros(1, N);
PhErr = zeros(1, N);
error_integral = zeros(1, N);
Theta = zeros(1, N);
% Loop Filter Coefficients
BW = 200;  % Hz
loop_theta = 2*pi*BW;
C1 = 4*(loop_theta)^2/(1+sqrt(2)*loop_theta+loop_theta^2);
C2 = 2*sqrt(2)*loop_theta/(1+sqrt(2)*loop_theta+loop_theta^2);
for i = 2:N
    % Downconverting to Baseband
    bb(i) = rf_signal(i).*exp(j*2*pi*fc*i).*exp(j*Theta(i-1));
    % Filtering
    bb_f = filter(RRC, bb(1:i));
    I_f(i) = real(bb_f(i));
    Q_f(i) = imag(bb_f(i));
    
    % Slicing
    if I_f(i) > 0
        I_r(i) = 1;
    else
        I_r(i) = -1;
    end
    
    if Q_f(i) > 0
        Q_r(i) = 1;
    else
        Q_r(i) = -1;
    end
    
    % Error
    error(i) = I_f(i) .* Q_r(i) - Q_f(i) .* I_r(i);
    
    % Loop Filter
    error_integral(i) = error(i).*C1 + error_integral(i-1);
    PhErr(i) = error(i).*C2 + error_integral(i);
    
    % Phase Accumulator
    Theta(i) = Theta(i-1) + PhErr(i);
    
end
figure
subplot 221
plot(real(bb))
title('I Channel')
subplot 222
plot(imag(bb))
title('Q Channel')
subplot 223
plot(I_f)
title('I Channel Filter')
subplot 224
plot(Q_f)
title('Q Channel Filter')
figure; subplot 311; plot(error); title('Phase Error');
subplot 312; plot(PhErr); title('Loop Filter');
subplot 313; plot(Theta); title('Control Signal \theta');

Just to motivate you, look at these signals:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10422&stc=1

http://www.alteraforum.com/forum/attachment.php?attachmentid=10423&stc=1

--- Quote End ---

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BPSK Demodulation

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