--- Quote Start ---
Could you please check the circuit below if is correct?
--- Quote End ---
Since you cannot guarantee the state of the nCONFIG pin when the ST micro boots, you should have a pull-down, so that the FPGA is disabled until the micro enables it.
CONF_DONE and nSTATUS should have external pull-ups (or you can enable pull-ups on your micro pins).
You should have a source termination on your DCLK signal (back at the micro pin).
You need to double-check that the FPGA configuration pin voltages are compatible with your microcontroller (if they are all 3.3V, then they will be fine).
Make sure your design also includes a breakout of the FPGA JTAG signals to a standard 10-pin header. It will make debugging of your design simpler :)
Cheers,
Dave
Honored Contributor
