Books for learning Verilog and SystemVerilog

I'm reading a Kindle version of a book by Janick Bergeron called "Writing Testbenches Using SystemVerilog". I haven't gone too far through but it seems to be a decent book. When I purchased it there were not many books on the subject with a good rating so that's why I went with it.

For synthesis this one was pretty good: http://www.amazon.com/verilog-hdl-synthesis-practical-primer/dp/0965039153/ref=sr_1_13?s=books&ie=utf8&qid=1334865289&sr=1-13

In general I would just use the books as a guide and just google search for examples. There are plenty of styles and techniques out there so you may not want to stick to whatever the author uses.