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Altera_Forum's avatar
Altera_Forum
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12 years ago

Board testing problem for FIR filter

Hi everyone,

I'm testing a Band Pass Filter generated by altera IP core (FIR compiler) on the board having Stratix 5 device 5SGSMD5K2F40C2 . I have written a small top entity for the BPF where in I have assigned the ast_source_data to a signal in the BPF component instantiation. And then I have assigned that signal to an output port. In simulation it's giving correct output but on board when checked in the signal tap analyzer tool, it's showing that the particular signal is zero and the output port has some junk values but the output valid is high even though that source data signal is zero on the board. Why is this happening when it was perfect in the simulation. Kindly reply me..

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Lawee,

    There is 1 critical warning. That's "The output clock port on PLL must be connected". . But actually I haven't used this clock anywhere in the BPF. It's used for another design so I just generated.