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Altera_Forum
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12 years ago

Board testing problem for FIR filter

Hi everyone, I'm testing a Band Pass Filter generated by altera IP core (FIR compiler) on the board having Stratix 5 device 5SGSMD5K2F40C2 . I have written a small top entity for the BPF wh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Lawee,

There is 1 critical warning. That's "The output clock port on PLL must be connected". . But actually I haven't used this clock anywhere in the BPF. It's used for another design so I just generated.