Honored Contributor
Honored Contributor"4.) When communicating with pll outputs and clock inputs on differential 3.3v what levels should I expect? 0V to 3.3V in phase and out? On one clock input I currently have -400mv to plus 3.6V and I can not find out why. the device feeding the signals in is set to 3.3V and bar a series DC blocking capacitor ( I know this generates negative volts ) I should still have 3.3V max! this may make my FPGA sick."
The overshoot of the signals due to reflection might lead to the 3.6V. This is generally due to impedance mismatch on the trace. You can double check on this by running IBIS model simulation to check the signal integrity.
