--- Quote Start ---
Assuming that the I/O problems are solved somehow, I still do not understand how is it possible for a 2ns BRAM to feed the I/O subsystem at 2.3Gs/s.
Even if I "go wide" how can I have the data retrieved from the BRAM faster that 500Ms/s for arbitrary Frequency Tunning Words (FTW) ?
In DDS the SRAM access is sequential, but it happens at arbitrary address increments...
--- Quote End ---
Work backwards from the output;
* 14-bit output at 2.3GSps
* 2 x 14-bit LVDS signals, double data-rate, at 1.15GSps
* LVDS transmit serialized in say x8 mode, sending bits to 14 LVDS channels, at 1.15/8 = 143.75MSps
* 14 x 8-bit width or 8 x 14-bit RAMs for the sample look-ups
The FPGA logic needs to implement a decimated NCO, where the decimation factor is the LVDS serialization factor. The decimation ultimately means you have to duplicate the NCO logic in the FPGA, so that you can simultaneously 'look-up' multiple NCO entries for a given FTW, and then serialize those entries.
To understand the concept, start off with an NCO driving a DAC at Nyquist rate. The try a demux-by-2 setup, then demux-by-4, etc. The pattern of logic will become clearer.
Cheers,
Dave
Honored Contributor
