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Altera_Forum
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13 years ago

BlockRAM performance for 2.3Gs/s DDS AWG

Which of the Altera products has sufficient BlockRAM performance to be suitable for a DDS AWG data source for the MAX5879 DAC (14bits @ 2.3Gsps) ? The data generated in the FPGA should upd...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Assuming that the I/O problems are solved somehow, I still do not understand how is it possible for a 2ns BRAM to feed the I/O subsystem at 2.3Gs/s.

Even if I "go wide" how can I have the data retrieved from the BRAM faster that 600Ms/s for arbitrary Frequency Tunning Words (FTW) ?

In DDS the SRAM access is sequential, but it happens at arbitrary address increments...