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Which of the Altera products has sufficient BlockRAM performance to be suitable for a DDS AWG data source for the MAX5879 DAC (14bits @ 2.3Gsps) ?
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Its not the RAM you need to care about, its the I/O interface.
From the Maxim web page:
the device has four 14-bit, multiplexed, low-voltage differential signaling (lvds) input ports that each operates up to 1150mwps. So you need an FPGA with 1.15Gbps LVDS. The Stratix series devices can operate at this data rate, so you will need to use one of them.
Here's a design that uses 1Gbps to an ADC interface. The DAC will be similar:
http://www.ovro.caltech.edu/~dwh/carma_board/ (
http://www.ovro.caltech.edu/%7edwh/carma_board/)
Cheers,
Dave
Honored Contributor
