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Altera_Forum's avatar
Altera_Forum
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18 years ago

Bit extending when adding

Hello, I'm trying to add an signed std_logic_vector(21 downto 0) with a std_logic (unsigned) using the vhdl operator "+". I'm using the "IEEE.std_logic_signed.all" library . I just assumed that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

That's exactly my point - use signed / unsigned types where it matters and adds clarity to the code. For most instances though, a data vector is neither signed nor unsigned - if it doesn't make a difference then use std_logic_vector.

Each to their own though.