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Altera_Forum
Honored Contributor
Honored ContributorBit extending when adding
Hello, I'm trying to add an signed std_logic_vector(21 downto 0) with a std_logic (unsigned) using the vhdl operator "+". I'm using the "IEEE.std_logic_signed.all" library . I just assumed that...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Does it make sense to keep converting an address to a std_logic_vector when it really is an unsigned representation of a number? --- Quote End --- Personally I would say yes - signed / unsigned are only high level human interpretations of the binary number. In most applications signed / unsigned doesn't really matter - it doesn't change what the value means but it does interfere when you want to interface to std_logic_vector. Why add an unnecessary constraint onto the data type? Sure use signed / unsigned but only when it's absolutely imperative that you capture the signed / unsigned nature of the signal and I've found that this is very rarely.
