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Altera_Forum
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18 years ago

Bit extending when adding

Hello, I'm trying to add an signed std_logic_vector(21 downto 0) with a std_logic (unsigned) using the vhdl operator "+". I'm using the "IEEE.std_logic_signed.all" library . I just assumed that...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

It's better to extend the bit sign instead a zero.

Use the numeric_std library.

--Extensión de signo

adder_in_a(2*N+Ncounter downto 2*N)<=(others=>mult_out(2*N-1));

adder_in_a(2*N-1 downto 0)<=mult_out;

--El sumador

adder_out<=std_logic_vector(signed(adder_in_a)+signed(acc_out));