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Altera_Forum
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18 years ago

Bit extending when adding

Hello, I'm trying to add an signed std_logic_vector(21 downto 0) with a std_logic (unsigned) using the vhdl operator "+". I'm using the "IEEE.std_logic_signed.all" library . I just assumed that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

There are a few quirks with numeric_std which take a bit of getting used to if you've been using std_logic_signed.

E.g. if you're incrementing a std_logic_vector by integer 1 with std_logic_signed: 

my_vector <= my_vector + 1;

if you use numeric_std then you have to do a bit of casting: 

my_vector <= std_logic_vector(      signed(my_vector) + 1     );

At first I found this a bit laborious but once I got used to it I actually found that it made the code clearer and easier to mix signed and unsigned operations in the same source file.

Good luck.