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Altera_Forum
Honored Contributor
Honored ContributorBit extending when adding
Hello, I'm trying to add an signed std_logic_vector(21 downto 0) with a std_logic (unsigned) using the vhdl operator "+". I'm using the "IEEE.std_logic_signed.all" library . I just assumed that...
Altera_ForumHonored Contributor
Honored ContributorThank you for the input. I'll take a look at the numeric_std library. Not beeing able to multiply std_logic_vectors with std_logics is not a large problem when designing something new. For the moment I will do like this:
p_value_rounded <= sxt(p_value_truncated,23) + p_value_carry_ext;
