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Altera_Forum
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17 years ago

Bit extending when adding

Hello, I'm trying to add an signed std_logic_vector(21 downto 0) with a std_logic (unsigned) using the vhdl operator "+". I'm using the "IEEE.std_logic_signed.all" library . I just assumed that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thank you for the input. I'll take a look at the numeric_std library. Not beeing able to multiply std_logic_vectors with std_logics is not a large problem when designing something new. For the moment I will do like this: 


p_value_rounded	<= sxt(p_value_truncated,23) + p_value_carry_ext;

where p_value_carry_ext is p_value_carry extended with a zero just to be on the safe side with the sign.

Best Regards,

Ola Bångdahl