Bit extending when adding

Hi Bango

In the std_logic_signed package the returned std_logic_vector is the same width as the input vectors. If you want the overflow then you could tweak your code thus:

p_value_rounded    <= (p_value_truncated(p_value_truncated'left) & p_value_truncated) + p_value_carry;

The general advice that goes with std_logic_signed is use numeric_std instead. std_logic_signed isn't a standard package - it certainly isn't an IEEE package and is only compiled into that library as a result of naughtiness. Appraently there aare differences between the Mentor and Synopsis std_logic_signed (and unsigned) packages. If you want a standard package use numeric_std which is an IEEE package. Also this makes it easier to use signed and unsigned in the same source code without confusion.

The downside that you will find is that there doesn't seem to be a "std_logic_vector + std_logic" function in numeric_std - there's everything else but this.

Hope this helps.