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Altera_Forum
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14 years ago

Binary format for Stratix IV Image in a NOR CFI Flash?

My application requires that a host system can write a new FPGA image into an on board Nor Flash (CFI intel P30 style 16 bit flash). Without using a JTAG pod, or Quartus Programmer. Instead...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Great information. I have the same configuration. Flash connected to cpld and uses the PFL to configure the fpga at power up. In the fpga code I've added the ability to connect the fpga IO lines to the flash (of course disconnect from cpld) and have memory mapped the flash into my pcie memory space. I used the tristate controller and tristate bridge to connect the Avalon bus to the flash IO pins. (BAR2 starting address 0x0) I have some questions.

When you use od to dump the rbf file I'm assuming the * are gaps in the file?

So after I erase the entire flash, do I program the flash by writing the rbf file starting at flash address 0x0 and increment the address every write cycle? (Assuming I'm using the slow write one word at a time method for my question.)