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Unfortunately, it is not very useful.
There are many SV features implemented, but not mentioned in the documentation. And viceversa, some features are documented as implemented, but they are really not.
The only conclusive way I found, is to just try.
And the Quartus documentation doesn't cover ModelSim at all. Quartus does support packed arrays on ports, it is the Altera version of ModelSim the one that doesn't.
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You are completely right.
package definition;
typedef struct packed {
logic a;
logic b;
} fraction;
typedef struct packed{
logic [3:0] scfsi;
fraction [1:0] gr;
} kkk;
endpackage
Compiling above example, I got this error:
"error (10168): systemverilog declaration error at aaa.sv(11): prefix for packed array type does not refer to a packable type". Although fraction is declared as an packed structure. Quartus 8.0 seems not to support packed union inside an packed structure and packed array of packed structures as well.
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