Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- Actually, I am using SystemVerilog and it can remove this restriction. --- Quote End --- Note that the ModelSim version provided by Altera has limited SV support. In particular it doesn't support unpacked arrays on module ports. The different SV support between Quartus and ModelSim can be a PITA. This is supposed to change in 8.1, when Quartus would upgrade ModelSim to a much newer version.