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It's very unclear from your post, what you are trying to achieve. Data "transfered between modules" would imply internal signals but no I/O pins at all, either if they use register cells, embedded memory or virtual signals (wires) only.
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I am sorry about that, I have little knowledge about using Quartus II and FPGA design.
Embedded memory could be the best suitable for my project, but would you please explain
the others ( register cells and wires) as long as they imply no I/O pins. Thanks.
PS: I don't know how to make them imply no I/O pins.
Honored Contributor
