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Altera_Forum's avatar
Altera_Forum
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9 years ago

Big IC delay timing

Hi guys! I'm using Cyclone V FPGA and have some probles with timing. There are some faling path with IC delay above 11ns (it's seem that this the reason). In my design I use 2 clocks: 100MHz and 200M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

You can resolve this problem using "set_malticycle_path end" constraint for SDC to set both setup and hold edge.

set_multicycle_path -end -setup -from [get_cells FF1] -to [get_cells FF2] N

set_multicycle_path -end -hold -from [get_cells FF1] -to [get_cells FF2] N-1

or using more than 2 FFs in this path, and set false_path constraint to SDC.