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Honored Contributor
Honored ContributorBig IC delay timing
Hi guys! I'm using Cyclone V FPGA and have some probles with timing. There are some faling path with IC delay above 11ns (it's seem that this the reason). In my design I use 2 clocks: 100MHz and 200M...
Altera_ForumHonored Contributor
Honored ContributorI have used DC FIFO for crossing clock domain. It's seem the problem solved
