I can't make it happen. Have a look at the attachment for the results.
Basically, it should just be a mechanical switch i.e.
when en = 0, wire A should be connected to wire C.
when en = 1, wire B should be connected to wire C.
-- The idea is that choose either A or B is exclusively
-- connected to C
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bidir_SPI_switch is
port(
A_SCLK, B_SCLK, C_SCLK : INOUT STD_LOGIC;
en, S : IN BIT
);
end bidir_SPI_switch;
architecture behaviour of bidir_SPI_switch is
begin
process(en,S)
begin
-- MASTER enable
if en = '0' then
A_SCLK <= C_SCLK;
B_SCLK <= 'Z';
C_SCLK <= A_SCLK;
else
-- SELECT either A or B
A_SCLK <= 'Z';
C_SCLK <= B_SCLK;
B_SCLK <= C_SCLK;
end if;
end process;
end architecture behaviour;