Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHi Epis,
IMO problem is that VHDL simulator can't handle the 'Z' state. In real world , I assume that your SDIO pin is pullup'ed. There is a way to simulate this behavoiur in VHDL, you should use 'H' state (instead of 'Z') , which stand for 'Weak one' . The VHDL resolution function will then , for example, handle the case where an external '0' is applied on your SDIO 'H' state : in this case, the result would be '0'. More help here : http://www.csee.umbc.edu/help/vhdl/misc.html I used this to simulate an I2C bus transaction (SDA and SCL are also bidir lines), it works nice, at least using Modelsim simulator. Warm regards.