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Altera_Forum
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14 years ago

Bidirectional buffer

Hi, I am working on Altera FPGA. Please help me to code a Bidirectional bus using HDL. Can anyone share a code for this. Regards, freak
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Altera_Forum
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12 years ago

Hi, I have a case similar to the code above. However, during gate-level simulation, while io_data has 'Z' values, data_in has 'X' value when data_out_ena is not '1'. What could probably cause the simulation to be behaving in this way?