Bidirectional buffer

For example, this could be a sample code for VHDL

(I wrote it without checking for syntax errors, be warned)

entity io_buffer is

port ( data_out : in std_logic_vector(WIDTH-1 downto 0);

data_in : out std_logic_vector(WIDTH-1 downto 0);

data_out_ena : in std_logic;

io_data : inout std_logic_vector(WIDTH-1 downto 0) );

end io_buffer;

architecture arch of io_buffer is

begin

bidir_buffer : process (data_out_ena, io_data)

begin

if (data_out_ena = '1') then

io_data <= data_out;

else

io_data <= (others => '0');

end if;

data_in <= io_data;

end process bidir_buffer;

end arch;