Best place for termination resistor

I am connecting a Micrel Gig-E PHY to a Cyclone III FPGA. Most of it is fairly straightforward - and I've got all GMII interface routed cleanly.

The only trick is the TXCLK/GTXCLK pin. It's a shared I/O pin on the PHY. In MII mode (10/100) the PHY transmits a 2.5MHz or 25MHz clock back to the FPGA. In GMII mode (1000), the FPGA transmits a 125MHz clock to the PHY.

To simplify matters, I've allocated two pins for the clock - one for the 125MHz output clock (GTXCLK), and a dedicated clock-in pin for the MII clocks (TXCLK). In GMII mode, I drive GTXCLK, and in MII mode, I tri-state it. I'm using the link activity indicator for 1000 mode to do the switching, under the assumption that the indicator will only be valid when the PHY is gigabit mode.

The dedicated clock-in always sees a clock, but in GMII mode, I can ignore it. This should allow the MAC core to think it has separate I/O lines.

The question is where to place the source terminating resistor. I know the best place would be right next to the output pin, but the trace runs under the FPGA. Right now, the resistor is right past the dedicated clock input pin, as it leaves the FPGA to the PHY. The clock line actually runs through the dedicated clock-in pad.

Is that going to be a problem? The only alternative is to drop to the bottom layer, pass through the resistor, and then pop back up to the top layer. There is way too much congestion to go around.

I know it sounds a bit anal, but I can't afford too many respins. I'm trying to get the "first" board as perfect as possible.

Thanks!