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Don't forget signaltap could be very useful.
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In my experience, signaltap has been an invaluable tool. Having a much more hardware background, I like to prototype as much as possible on development kits, and use signaltap to monitor any important signals. This can be done in small "modules" which then build a much more complex system.
Ensuring clock synchronization is also quite helpful. Sometimes if there are signals crossing clock domains, you can use a simple D flipflop in between domains to gate the timing. Quartus has a much easier time doing the timing analysis then.
The RTL viewer can also help identify timing glitches in the synthesizer. I have had circumstances where state machines were being reset in places where the code should not have allowed it, but a race condition identified with the RTL viewer allowed me to change the code so the race condition no longer existed.
My last advice is to use the built in timing tools in Quartus. You can do a lot with optimizing for speed vs. area, and using logic lock regions on any timing-critical modules.
Honored Contributor
