Forum Discussion
Altera_Forum
Honored Contributor
16 years agoApart from timing, there are other important issues that result in hardware/simulation mismatch:
1) startup values on registers. Best to have reset values on all registers. 2) wrong simulation input vectors that do not represent actual inputs as to pattern and relative relations. i.e. simulation was false pass... include also any floating nonconnected inputs. 3) loss of data flow control e.g. overfilling or underfilling of buffers. This may be difficult to simulate with finite vectors. 4) hardware issues e.g. clock jitter. floating pins. A proper standard testbench is important. The testbench itself must be dead simple so that you don't have to test your testbench. For hardware, make extensive use of alarms (to LEDs...) to help you localise the issues.