Beginner device CPLD/FPGA selection for anti-aliasing filter

Hey FvM,

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An economic implementation would e.g. use a 4:1 CIC decimator and a higher order FIR filter for the last decimation stage. In any case, there's a tradeoff between filter transition steepness and required filter complexity.

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I haven't had to implement FIRs at such low frequency. Once you get to having a serial filter, the FIR becomes a RAM with coefficients and a multiplier, or a MACC circuit. Given that 1k-samples of coefficients will fit in an FPGA RAM block easily enough, would you bother adding the complexity of a CIC followed by cleanup FIR? Seems like more trouble than its worth ...

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Did you notice that audio ADCs respectively codecs have nearly perfect anti-aliasing filters and decimation down to an intended sampling rate, partly even programmable.

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This could be a better solution than using an ADC+FPGA+uC; find an ADC that already includes the digital signal processing you need and interface that to the micro.

FvM - Do any particular codec part numbers come to mind?

Cheers,

Dave