BCD counter vhdl code

thanks for ur explanation and assist.. understood a lot!

"By slightly increasing the pulse width of load, it should work also in functional simulation." could you explain it more ? how do u increase the pulse width of load.

http://i53.tinypic.com/2lbkkrt.png

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity d4 is

port (reset, sensor, load :in std_logic;

p :in std_logic_vector (4 downto 0);

led_on :out std_logic;

q :out std_logic_vector (4 downto 0));

end d4;

architecture flow of d4 is

signal count_sig : unsigned (4 downto 0);

begin

process (sensor, reset, load, p)

begin

if (reset = '1') then

count_sig <= "00000";

elsif rising_edge (sensor) then

count_sig <= count_sig + 1;

if (count_sig = 31) then

led_on <= '1';

count_sig <= (others => '0');

else

led_on <= '0';

count_sig <= count_sig + 1;

if (load = '0') then

count_sig <= unsigned(p);

end if;

end if;

end if;

end process;

q <= std_logic_vector (count_sig);

end flow;

looking better now.

but

if (load = '0') then

count_sig <= unsigned(p);

this code seems useless..

When load is '0' on P=2 .. q is not starting from 2... or when load is '0' on P=20.. q is not starting from 20, like shown in the correct stimulation. please enlighten me. i have been saying countless times of thank you but really i appreciate ur help..

happy lunar new year to all of u!