expected result
http://i54.tinypic.com/2zp2p3p.png
my result http://i51.tinypic.com/al6iyc.png library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d4 is
port (reset, sensor, load :in std_logic;
p :in std_logic_vector (5 downto 0);
led_on :out std_logic;
q :out std_logic_vector (5 downto 0));
end d4;
architecture flow of d4 is
signal count_sig : unsigned (5 downto 0);
signal load_sig : unsigned (5 downto 0);
begin
process (sensor, reset, load, p)
begin
if (reset = '1') then
count_sig <= "000000";
elsif rising_edge (sensor) then
if (count_sig = 32) then
led_on <= '0';
count_sig <= "010000";
else
led_on <= '1';
count_sig <= count_sig + 1;
if (load = '0') then
count_sig <= unsigned(p);
end if;
end if;
end if;
end process;
q <= std_logic_vector (count_sig);
end flow;
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When load is '0' on P=2 .. q is not starting from 2... why???
btw LED is kind of correct now. no idea why is it '0' when q = 0..
sorry for the troubles guys please help me ..