bandwidth for Cyclone IV(-8 grade) and 32-bit DDR2 SDRAM

In general is sounds ok. Be careful on bank usages.

Unless the DDR2 and ADC use the same IO voltage, they will require different banks, so you'll have some wasted IO's due to this limitation.

If you are using LVDS there are rules associated with these IO's around and adjacent single ended IO's as well.

My recommendation is you complete a top level design back box that connects all the IO's that will be used, and has minimal logic to insure the IO's are not optimized out.

DDR2 timing can be difficult, so the -8 speed grade may give you difficulties here. (I haven't played with that side much).. (Much easier with Cyclone V with the hard memory controllers)

Your size requirements really depends on what else you need to do in the device. If you can do the entire design and have plenty of resources left over you are good, but designs tend to grow over time, so I tend to pick the middle family size for a targeted package is I think I'm IO limited, but make sure the board is capable of migrating up and down for the device family.

This is not as easy as it appears, Many of the "Migration" paths have IO that are either VCC/GND pins or NC pins when you migrate up and down. So you want to closely look at all package family members to make sure you have it right, and have the migration devices selected in your pinout as well in quartus.

If this is just a one-off or small number of boards, it may be much easier to get what you need by building a daughter card using the HSMC connectors for your ADC's and using an off the shelf dev board like the SOC kit that already has the ram and interfaces you need.

Pete