Avalon OpenCores Ethernet MAC and QII version 10 and higher

So, I've been messing around with the design of the opencore mac for Qsys and at least I'm able to recieve frames now, alltough tx is not yet working; here is me little patch to eth_avalon_rxdma.v. First there is the new conception of av_waitrequest; I just removed the condition from the av_write set. Also I've seen the RX_EOP coming up and going down before the FIFO captured it, so I changed the lines at the end ...

I'm new to HDL/FPGA design ... does this make sense to you? Is it just working by luck?

diff -u ../eth_ocm//eth_avalon_rxdma.v eth_ocm//eth_avalon_rxdma.v

--- ../eth_ocm//eth_avalon_rxdma.v 2010-02-05 12:07:22.000000000 +0100

+++ eth_ocm//eth_avalon_rxdma.v 2011-11-22 00:24:58.498985534 +0100

@@ -217,7 +217,7 @@

always @(posedge clk or posedge reset)

if(reset) av_write <= 1'b0;

- else if(~av_waitrequest)

+ else

av_write <= pre_av_write;

always @(posedge clk)

@@ -577,16 +577,17 @@

//We'll alow these to overrun

-always @* begin dff_stat[MBYTE_BITS] = rx_state[RX_EOP ];

- if(rx_state[RX_EOP]) dff_stat[MBYTE_BITS+1] = rx_abort_r;

- else dff_stat[MBYTE_BITS+1] = 1'b0;

+always @* begin

+ if(rx_state[RX_EOP]) dff_stat[MBYTE_BITS+1] <= rx_abort_r;

+ else dff_stat[MBYTE_BITS+1] <= 1'b0;

end

-always @(posedge rxclk)

+always @(posedge rxclk) begin

+ dff_stat[MBYTE_BITS] <= rx_state[RX_EOP ];

if(rx_dv) begin dff_din_reg[rx_bcnt] <= rx_data;

dff_stat[0+:MBYTE_BITS] <= rx_bcnt;

end

-

+end