Honored Contributor
Honored ContributorOK for the signal integrity.
Another question is about the topology of the bus I proposed : Is there a problem to use the Avalon Bus which is the processor Bus (transmit data between processor and his external SRAM) to access to the slave cards (as an extension bus in reality) ? Unless, I would rather use 2 Avalon Master MM : One for Bus Processeur (Nios2, UART, SRAM, GPIO, ...) and 1 for extension bus through the backplane ? Is it a better solution ? Actually, a more conventional solution would use the Avalon bus as the processor Bus and have a Brige Avalon - PCI for example to access the slave cards ? However, it complicates my design .... Some comments, please ... Nicolas.
