Avalon on a backplane ??

Thank you for your answers.

My application doesn't need a high throwput because the Master will only have to send commands to and receive status from the slaves cards. However, the clock in the FPGA which wll driver the Avalon bus is 25 MHz so like Josyb said, I have to worry about signal integrity. Josyb, do you have any advice for nice impedance controlled boards and suitable connectors for this application. For connectors, I thought about using cPCI connector but I don't know how to do the impedance adaptation on the master Bord and on the slave boards.

To my mind, as there is only 1 Master and that the Avalon bus offer one Data Bus for write operation (writedata) and one Data Bus for read operation (readdata), I think that I only have to implement a tri-state register in the Slave CPLD on the readdata bus. I have posted a JPG file of the topology of the bus. Do you agree with this ?

Finally, have you heard about any previous project that have chosen this architecture with a Avalon Bus in the Backplane. Maybe, any revendors of FPGA board that can be usefull for me for this application of Avalon Backplane.

Nicolas.