Avalon on a backplane ??

There are a few trade-offs to consider. One is the overall bandwidth. If the CPLD cards are have a reasonable low throughput and you do not have many of them, say 8 pcs or so, a general bus is feasible. On the other hand if you have a large IO throughput you may be better off to connect the CPLD cards in a star fashion where every CPLD board has its own dedicated high-speed channels to and from the main FPGA-board. Another option is to daisy-chain the bus, where every card retransmits the signals left and right.

The other one is signal integrity. This is much harder for a bus than for point to point connections, especially if you have to achieve a high throughput. Point to point connections can use series termination, either incorporated in the IO-cell of the FPGA, or just a small external 39 ohm resistor. A bus needs parallel termination at both sides, presenting a 25 ohm load to drive by the cards. Bear in mind that not the frequency of the clock is dominant but rather the rise and fall times of the signals. Modern FPGAs are fast things with fast edge rates ... So you have to make nice impedance controlled boards and use suitable connectors.

Point to point systems can use Source-Synchronous signalling where a broadside bus needs a master clock defining all transactions. But at a low clock speed this is quite manageable.

In stead of using a CPLD on the slave cards, I assume you are thinking of using MAX II devices, it may be a better idea to use small Cyclone III or IV devices and load/configure these from the master FPGA board.