Avalon MM Slave waitrequest signal modus-operandi

The problem is most likely you are deasserting waitrequest too late. Since waitrequest is a register and you assign it 1'b1 in a clocked process statement that means during the command phase of the read waitrequest is still low and as a result the read is accepted, and then on the next clock edge your waitrequest becomes high. By the time it's high the read is over so that's causing you to get out of sync.

The fix should be as simple as something like this:

1) Rename "waitrequest" to busy (keep it a register though)

2) Create a new waitrequest but just make it an output wire instead of a register

3) Assign waitrequest like this: assign waitrequest = read | busy;

What this does is make sure you cover the cycle when the read is being issued.

That all said I wouldn't implement the hardware like this. What I would do instead is add a readdatavalid signal and just pipeline that with the result and not use waitrequest to throttle the transaction. That way if your hardware is fully pipelined you can have this logic handling multiple reads in flight.

Another alternative that should work if you want to stick to using waitrequest is to keep waitrequest high when there are no transactions in flight and only strobe it low when a result is ready. The Qsys fabric I'm told should not care if your component asserts waitrequest while your logic is being accessed so that would also get around the problem of your waitrequest transistioning too late. Still I would go with a more pipelined approach since that's a closer fit to a streaming approach where data is constantly poring in/out of the logic.

*just read your last post, if the hardware is always going to have a fixed latency then you can declare this in the .tcl file and all you have to do is make sure the result shows up on readdata 'x' number of cycles after the read is accepted and not bother backpressuring with waitrequest. This assumes your logic can handle back to back read request, if your logic really is fixed latency and pipelined then this should be the case.