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Altera_Forum
Honored Contributor
11 years agoThanks, BadOmen, for replying.
As requested, here follows the code for the Avalon Interface:
module sum_of_squares_inst
(
input clk,
input rst,
input write,
input read,
input addr,
input writedata,
output reg waitrequest,
output reg readdata
);
reg a, b;
wire r;
reg start;
wire done, clk_en;
sum_of_squares_control sosctrl
(
.clk(clk),
.clk_en(clk_en),
.rst(rst),
.start(start),
.done(done)
);
sum_of_squares sos
(
.clk(clk),
.clk_en(clk_en),
.a(a),
.b(b),
.r(r)
);
initial begin
a <= 32'h00000000;
b <= 32'h00000000;
readdata <= 32'h00000000;
start <= 0;
waitrequest <= 0;
end
always @(posedge clk) begin
if(rst) begin
a <= 32'h00000000;
b <= 32'h00000000;
readdata <= 32'h00000000;
start <= 0;
end else begin
if(done & !start) //If there is no process working, the module is read to be read or written
waitrequest <= 0;
if(write) begin
case(addr)
2'b00: begin // Write to the first register
a <= writedata;
start <= 0;
end
2'b01: begin // Write to the second register
b <= writedata;
start <= 0;
end
2'b10: begin // Write to the start register
if(writedata) begin
start <= 1; // One cycle wide control signal
waitrequest <= 1; // Wait for the process to finish
end else
start <= 0;
end
default: begin
a <= 32'h00000000;
b <= 32'h00000000;
start <= 0;
end
endcase
end else if(read) begin
case(addr)
2'b00: // Read the result
readdata <= r;
default:
readdata <= readdata;
endcase
end else
start <= 0;
end
end
endmodule
The other two modules are very simple, than I'll not post their codes here. This is what them do: sum_of_squares is the arithmethical unity. It does a fp multplication of the two registers values in parallel, then sums the results. Multiplication takes 5 clocks, sum takes 7, plus 1 to save in the result register, total latency 13 clocks, fixed. sum_of_squares_control is a FSM that receives the start control signal then generates the clock_enabled signal and counts the 13 clocks necessary to get the expected result and save it in the result register. It also controls the state of the done signal, that indicates if the unity is working or is idle. I can't generate the simulation right now, because I am running Linux now and modelsim is crashing since I upgraded Quartus to 14.0.2. Later, I'll run the Windows version and attach the simulation, but as I said before, the waitrequest signal rises and falls when it should be. In the future, the final module will be much more complex, then a Streaming interface seems more fit. If you can indicate me some material or reference design to help me with this, I'll be grateful. Thank you again for the help! Regards, Thank you again for the