ContributorAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP - Hard Reset to Soft Reset
Dear Intel,
Really having a hard time on switch to soft reset.
According to datasheet and forum discussion.
Hard reset on the hard PCIe require a specified pin or pins to work.
In order to fully make use all LVDS pairs inside the same bank of the hard PCIe reset pin, it is a must to use soft reset.
Under testing the hard reset pin can function properly on root port design.
Once we changed to soft reset under xxxx.qsys:
<parameter name="force_src" value="1" />
After loading the driver on linux via insmod xxx.ko
It immediately stuck.
The reset is based on
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/PCIe_Hard_IP
assign pcie_npor_pin_perst = pcie_reset ? ~pcie_reset : 1'bz;
assign pcie_npor_npor = hps_fpga_reset_n & pcie_npor_pin_perst
.pcie_cv_hip_avmm_0_npor_npor (pcie_npor_npor),
.pcie_cv_hip_avmm_0_npor_pin_perst (pcie_npor_pin_perst),
"pcie_reset" signal is generated by PIO IP
Thanks,
Brian
Ok the solution to resolve SRC under Hard PCIe RP:
The example from rocketchip and MitySOM gate the mgmt reset by nreset_status.
Due to pin_perst is not used -> 1'b1
The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset bynreset_status will dead lock and never exit the reset.
