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fvult
New Contributor
New ContributorAvalon-MM Arria V Hard IP for PCI Express Intel FPGA IP: waitrequest high
We evaluate the performance of the PCIe IP with Avalon MM interface on the Arria V FPGA. We only achieve a data rate of 1400*10^9 bytes per second which is less than written in the "PCI Express High ...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
To understand the issue more , kindly let me know which wait request you are mentioning , for Avalon MM there are more than one waitrequest signal. so kindly let me know which specific waitquest signal you are mentioning.
If you can let me know with respect to the block diagram mentioned , that will be great.
Page no:140
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-01105-1_6.pdf
fvultSignal TxsWaitRequest_o in Figure 7–34 on page no 139
