avalon memory mapped protocol

Hi,

Even If I do as you say, I may still have long paths, simply because of the distance between the source of the wait_request signal to the desitination of the wait_request signal (which is probably near a memory element which has fixes locations.(assuming high clock frequencies)

This may be even more difficult in case the source of the wait_request signal is logic-locked to certain location which is remote from the destination of the wait_request signal.

If there whould be a wait_request latency(at least for the pipeline mode) like in the avalon streaming protocol, the master could treat the wait_request signal at more ease(sampling it to ensure timing), since it has some spair clocks in which it could still send data.