avalon bus, miss reading data

Hi all,

I have a Verilog RTL design which perform polynomial reconstruction. This hardware functional unit is activated by 'start' signal and gives 'done' signal once it has finish it computation.

The hardware functional unit is running at 50MHz, and from the simulation waveform, it takes around 17.16us (see attachment) to finish computation, which is about 50M*17.16u, 858 cycle count. However, when I integrate the hardware functional unit into embedded system and download onto Stratix II, the computation time I get is roughly 8M (see Attachment). This make no sense.

Anyone has any idea what is the reason that cause different clock count?

Thanks and Regards,

ty6