Autostart NIOS from external SDRAM problem

Hi,

From the doc, there is a image on the "Hardware Design" shows the Platform Designer and the connections made of each IP. You can handpicked the IPs shown and connect them accordingly, which will get you the hardware design example.

Then follow the steps for the "Nios® II Processor Application Copied from EPCQ Flash to RAM Using Boot Copier" section.

I guess the first issue is to get the epcq controller to be your reset vector.

Then, back to your original issue, to try this example and build it up until the .jic programming file and program it to your board and tests.

With the .jic you can do a reset on your FPGA device using the reset button or power cycle.