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fvult
New Contributor
New ContributorAsync FIFO size in AVMM interconnect
We connect multiple AvalonMM masters to the Arria V Avalon MM PCIe IP. Qsys automatically creates an appropiate AVMM interconnect which looks as follows: Two Avalon masters (called dma_writer ...
SyafieqS
Super Contributor
Super ContributorHi Fabien,
Refer to link below FIFO Intel® FPGA IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf ( p3-Configuration Methods)
fvultThe FIFO is inside an AVMM interconnect that is automatically generated by Platform Designed (QSYS). Please refer to the image in the first post to study the setup.
