Forum Discussion

New Contributor

5 years ago

Async FIFO size in AVMM interconnect

We connect multiple AvalonMM masters to the Arria V Avalon MM PCIe IP. Qsys automatically creates an appropiate AVMM interconnect which looks as follows: Two Avalon masters (called dma_writer ...

SyafieqS

Super Contributor

5 years ago

Hi Fabien,

You can create and edit you own component for _hw.tcl file and have flexibility to control the parameter according to your desires. You cannot edit components installed with the Quartus II software, such as Altera-provided components Refer to link below for creating PD component.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf (p89- Creating Platform Designer Components).

Thanks,

Regards

Forum Discussion

Async FIFO size in AVMM interconnect

Recent Discussions

Cyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memory

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information