Async FIFO size in AVMM interconnect

Manually inserting Avalon-MM Clock Crossing Bridge IP did solve the problem but this solution complicates the design and uses more FPGA ressources.

Because the automatic generation of interconnects is the main feature of QSYS I would expect it to behave more intelligent. Based on what information does QSYS decide how deep the asyncronous FIFOs in the interconnect are? Is it possible to influence the FIFO depth be changing the parameters of the AVMM masters and slaves in the hw_tcl files?