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fvult
New Contributor
New ContributorAsync FIFO size in AVMM interconnect
We connect multiple AvalonMM masters to the Arria V Avalon MM PCIe IP. Qsys automatically creates an appropiate AVMM interconnect which looks as follows: Two Avalon masters (called dma_writer ...
SyafieqS
Super Contributor
Super ContributorHi Fabien,
Yes, the simplest what I could think to solve this issue right now is to implement Avalon-MM Clock Crossing Bridge IP. It transfers Avalon-MM commands and responses between different clock domain and parameters to control the depth of the command and response FIFOs in both the master and slave clock domains.
Thanks,
Regards
